CH32V006E8R6 Pinout (QSOP24)

CH32V006E8R6 is the CH32V006 in a QSOP24 package – 22 GPIO, 62 kB of flash and 8 kB of RAM. Panda used it, for example, in his PidiMet multimeter on breatharian.eu.

Compared with TSSOP20 it has four more pins (22 GPIO instead of 18) and doesn’t need to share PD7 with PA4 – but PA1 and PA6 are connected internally.

Specifications

RISC-V (QingKe) at 48 MHz
62 kB flash, 8 kB SRAM
22 GPIO, ADC, op-amp
2× USART, I2C, SPI, timers, PWM
3.3 V or 5 V supply
single-wire (SWIO) and two-wire (SWDIO + SWCLK on PB3) debugging
QSOP24 package

It is programmed with the WCH-LinkE – in MounRiver Studio, the Arduino IDE or with ch32fun.

Pinout and pin table

Hover over a pin in the diagram or a table row; use the filter to highlight a bus. You can download the pinout as PNG or SVG.

Download:PNG SVG

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Pin table – CH32V006E8R6
Pin	Name	Direction	UART	I2C	SPI	PWM	ADC	Remap	Note
1	PD1	input/output				T1CH3N		1: SCL, T1CH3N; 2: T1CH3N, RX; 4: SDA, T1CH4, TX; 5: T1CH4, RX, RX2	Programming and debugging (SWIO / SWDIO); ADC trigger (ADC_IETR); op-amp input +3
2	PC0	input/output				T2CH3		1: NSS, T2CH3; 2: T1CH3; 3: MOSI, TX; 4: T2CH1ETR; 7: T1CH1N; 9: T1CH1N
3	PC1	input/output		SDA	NSS			1: T2CH1ETR; 2: T1BKIN, T2CH4; 3: T1BKIN, T2CH1ETR, RX; 4: T2CH2; 5: NSS; 7: T1CH2N; 9: T1CH2N
4	PC2	input/output		SCL				1: ADC trigger (ADC_RETR), T1BKIN; 2: T2CH2, RTS; 3: T1ETR; 7: T1CH3N; 9: T1CH3N	USART RTS; T1BKIN
5	VSS	–
6	VDD	input							Power 3.3 V or 5 V
7	PC5	input/output			SCK			1: SCK; 2: SCL, T1ETR, T2CH1ETR; 3: T1CH3; 6: TX; 7: T1CH2; 8: T1CH2	Reset (NRST) by default – on QSOP24 the reset is here; usable as GPIO only after switching in the option bytes (RST_MODE = 11); T1ETR
8	PC4	input/output				T1CH4	A2	1: T1CH4; 2: NSS, T1CH2N; 3: T1CH1; 5: TX2; 6: NSS; 7: T1CH1; 8: T1CH1; 9: RX	clock output (MCO)
9	PD2	input/output				T1CH1	A3	1: T1CH1; 2: SCK, T2CH3; 3: T1CH2N, TX2; 8: CTS
10	PD3	input/output				T2CH2	A4	1: T2CH2; 2: MOSI, T1CH4; 3: RX2; 4: NSS; 7: T2CH1ETR; 8: RTS	USART CTS; ADC trigger (ADC_RETR); op-amp input +2
11	PD4	input/output				T2CH1ETR	A7	1: T1ETR; 3: T1CH4; 4: SCK, T1ETR; 5: T1ETR; 6: T1ETR; 7: T2CH2; 9: RTS	op-amp output 0
12	PD5	input/output	TX				A5	1: RX; 3: T2CH4; 4: MISO; 9: CTS
13	PD6	input/output	RX				A6	1: TX; 3: T2CH3; 4: MOSI
14	PD7	input/output				T2CH4		1: T2CH4; 4: CTS; 5: CTS	Ordinary GPIO – reset is on PC5 in this package; op-amp input +1
15	PA4	input/output						1: TX2; 5: CTS2	USART CTS2; op-amp input −2
16	PA5	input/output						1: RX2; 4: RTS; 5: RTS; 6: RX2	USART RTS2; op-amp output 1
17	PA1/PA6	input/output				T1CH2	A1	PA1 – 1: T1CH2; 2: RTS2; 3: RTS2; 4: RTS2; 5: SCK, T2CH2, RTS2; 6: T2CH2; 8: RX; 9: T1CH2 \| PA6 – 6: TX2	Shared pin – PA1 (OSCI crystal) and PA6 are connected internally, they must not both be outputs; PA1: A1, T1CH2, OSCI, op-amp input −0
18	PA0	input/output						2: CTS2; 3: CTS2; 4: T1CH1N; 5: T1CH1N, T2CH1ETR; 6: T1CH1N; 8: TX; 9: T1CH1, TX
19	PA2	input/output				T1CH2N	A0	1: ADC trigger (ADC_IETR), T1CH2N; 2: TX2; 4: T1CH2N; 5: MOSI, T1CH2N, T2CH3; 6: T1CH2N, T2CH3; 7: T2CH3; 9: T1CH3	Krystal (OSCO); op-amp input +0
20	PD0	input/output				T1CH1N		1: SDA, T1CH1N; 2: TX; 4: T1CH3N; 5: T1CH3N; 6: T1CH3N	op-amp input −1
21	PA3	input/output						2: RX2; 4: T1CH1; 5: T1CH1, T2CH4; 6: T1CH1, T2CH4; 7: T2CH4; 8: T1CH1N; 9: T1CH4
22	PB0	input/output						3: NSS; 4: T1CH2, TX2; 5: T1CH2; 6: T1CH2; 8: T1CH2N
23	PB1	input/output						3: SCK; 4: T1CH3, RX2; 6: T1CH3, T2CH1ETR; 8: T1CH3N
24	PB3	input/output	RX2					1: RTS2; 2: MISO; 4: SCL, T1BKIN, RX; 5: T1BKIN, TX; 6: RTS2	Serial wire debug clock (SWCLK)

What to watch out for

PD1 is the SWIO programming pin – leave it free.
In this package, reset (NRST) is on PC5 and is enabled from the factory – free it up as GPIO in the option bytes (RST_MODE = 11).
Logic levels follow the supply voltage (3.3 V or 5 V).
With an external crystal, PA1 and PA2 are taken – and along with PA1, so is PA6, which is connected to it internally (pin 17).