CH32V006 is the more capable sibling of the CH32V003: 62 kB of flash, 8 kB of RAM and two USARTs. It still runs at 48 MHz with the same simple programming via WCH-LinkE.
CH32V006F8P7 in the TSSOP20 package has a layout close to the CH32V003F4P6, except that PD7 and PA4 share pin 4.
Specifications
- RISC-V (QingKe) at 48 MHz
- 62 kB flash, 8 kB SRAM
- 18 I/O pins, ADC, op-amp
- 2× USART, I2C, SPI, timers, PWM
- 3.3 V or 5 V supply
- single-wire programming and debugging (SWIO on PD1)
- TSSOP20 package
The extra memory comes in handy for larger programs, displays or communication protocols where the CH32V003 runs out of room.
Pinout and pin table
Hover over a pin in the diagram or a table row; use the filter to highlight a bus. You can download the pinout as PNG or SVG.
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| Pin | Name | Direction | UART | I2C | SPI | PWM | ADC | Remap | Note |
|---|---|---|---|---|---|---|---|---|---|
| 1 | PD4 | input/output | T2CH1ETR | A7 | 1: T1ETR; 3: T1CH4; 4: SCK, T1ETR; 5: T1ETR; 6: T1ETR; 7: T2CH2; 9: RTS | op-amp output 0 | |||
| 2 | PD5 | input/output | TX | A5 | 1: RX; 3: T2CH4; 4: MISO; 9: CTS | ||||
| 3 | PD6 | input/output | RX | A6 | 1: TX; 3: T2CH3; 4: MOSI | ||||
| 4 | PD7/PA4 | input/output | T2CH4 | PD7 – 1: T2CH4; 4: CTS; 5: CTS | PA4 – 1: TX2; 5: CTS2 | Shared pin – PD7 and PA4, they must not both be outputs. PD7 is reset (NRST) from the factory: PA4 can be an output only after switching PD7 to GPIO in the option bytes (RST_MODE = 11); PD7: T2CH4, NRST, op-amp input +1; PA4: USART CTS2, op-amp input −2 | ||||
| 5 | PA1 | input/output | T1CH2 | A1 | 1: T1CH2; 2: RTS2; 3: RTS2; 4: RTS2; 5: SCK, T2CH2, RTS2; 6: T2CH2; 8: RX; 9: T1CH2 | Krystal (OSCI); op-amp input −0 | |||
| 6 | PA2 | input/output | T1CH2N | A0 | 1: ADC trigger (ADC_IETR), T1CH2N; 2: TX2; 4: T1CH2N; 5: MOSI, T1CH2N, T2CH3; 6: T1CH2N, T2CH3; 7: T2CH3; 9: T1CH3 | Krystal (OSCO); op-amp input +0 | |||
| 7 | VSS | – | |||||||
| 8 | PD0 | input/output | T1CH1N | 1: SDA, T1CH1N; 2: TX; 4: T1CH3N; 5: T1CH3N; 6: T1CH3N | op-amp input −1 | ||||
| 9 | VDD | input | Power 3.3 V or 5 V | ||||||
| 10 | PC0 | input/output | T2CH3 | 1: NSS, T2CH3; 2: T1CH3; 3: MOSI, TX; 4: T2CH1ETR; 7: T1CH1N; 9: T1CH1N | |||||
| 11 | PC1 | input/output | SDA | NSS | 1: T2CH1ETR; 2: T1BKIN, T2CH4; 3: T1BKIN, T2CH1ETR, RX; 4: T2CH2; 5: NSS; 7: T1CH2N; 9: T1CH2N | ||||
| 12 | PC2 | input/output | SCL | 1: ADC trigger (ADC_RETR), T1BKIN; 2: T2CH2, RTS; 3: T1ETR; 7: T1CH3N; 9: T1CH3N | USART RTS; T1BKIN | ||||
| 13 | PC3 | input/output | T1CH3 | 1: T1CH3; 2: T1CH1N, CTS; 3: T1CH1N; 4: T2CH3; 5: T1CH3 | |||||
| 14 | PC4 | input/output | T1CH4 | A2 | 1: T1CH4; 2: NSS, T1CH2N; 3: T1CH1; 5: TX2; 6: NSS; 7: T1CH1; 8: T1CH1; 9: RX | clock output (MCO) | |||
| 15 | PC5 | input/output | SCK | 1: SCK; 2: SCL, T1ETR, T2CH1ETR; 3: T1CH3; 6: TX; 7: T1CH2; 8: T1CH2 | T1ETR | ||||
| 16 | PC6 | input/output | MOSI | 1: MOSI, CTS; 2: SDA, T1CH1; 3: T1CH3N, CTS; 6: RX; 7: T1CH3; 8: T1CH3 | |||||
| 17 | PC7 | input/output | MISO | 1: MISO, RTS; 2: T1CH2; 3: T1CH2, T2CH2, RTS; 6: MISO, CTS; 7: T1CH4, CTS; 8: T1CH4 | |||||
| 18 | PD1 | input/output | T1CH3N | 1: SCL, T1CH3N; 2: T1CH3N, RX; 4: SDA, T1CH4, TX; 5: T1CH4, RX, RX2 | Single-wire programming and debugging (SWIO); ADC trigger (ADC_IETR); op-amp input +3 | ||||
| 19 | PD2 | input/output | T1CH1 | A3 | 1: T1CH1; 2: SCK, T2CH3; 3: T1CH2N, TX2; 8: CTS | ||||
| 20 | PD3 | input/output | T2CH2 | A4 | 1: T2CH2; 2: MOSI, T1CH4; 3: RX2; 4: NSS; 7: T2CH1ETR; 8: RTS | USART CTS; ADC trigger (ADC_RETR); op-amp input +2 |
What to watch out for
- Pin 4 connects PD7 and PA4 – use only one of them. PD7 is reset (NRST) from the factory, so only use PA4 as an output after switching PD7 to GPIO in the option bytes (RST_MODE = 11).
- PD1 is the SWIO programming pin – leave it free.
- Logic levels follow the supply voltage (3.3 V or 5 V).
CH32V articles on chiptron.eu/
These chiptron.eu/ articles cover the CH32V chips:
- CH32V003 in the Arduino IDE and on Linux – WCH-LinkE programmer, openOCD and the CH32fun alternative
More pinouts
See all pinouts on the Pinouts page.